View LTC3605_4412037.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

LTC3605 15V, 5A Synchronous Step-Down Regulator FEATURES
n n n n n n n n n n n
DESCRIPTION
The LTC(R)3605 is a high efficiency, monolithic synchronous buck regulator using a phase lockable controlled on-time constant frequency, current mode architecture. PolyPhase operation allows multiple LTC3605 regulators to run out of phase while using minimal input and output capacitance. The operating supply voltage range is from 15V down to 4V, making it suitable for dual lithium-ion battery inputs as well as point of load power supply applications from a 12V or 5V rail. The operating frequency is programmable from 800kHz to 4MHz with an external resistor. The high frequency capability allows the use of small surface mount inductors. For switching noise sensitive applications, it can be externally synchronized from 800kHz to 4MHz. The PHMODE pin allows user control of the phase of the outgoing clock signal. The unique constant frequency/controlled on-time architecture is ideal for high step-down ratio applications that are operating at high frequency while demanding fast transient response. Two internal phase-lock loops synchronize the internal oscillator to the external clock and also servos the regulator on-time to lock on to either the internal clock or the external clock if it's present.
L, LT, LTC, LTM and Polyphase are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 5847554, 6580258, 6304066, 6476589, 6774611.
High Efficiency: Up to 96% 5A Output Current 4V to 15V VIN Range Integrated Power N-Channel MOSFETs (70m Top and 35m Bottom) Adjustable Frequency 800kHz to 4MHz PolyPhase(R) Operation (Up to 12 Phases) Output Tracking 0.6V 1% Reference Accuracy Current Mode Operation for Excellent Line and Load Transient Response Shutdown Mode Draws Less than 15A Supply Current Available in 24-Pin (4mm x 4mm) QFN Package
APPLICATIONS
n n n n
Point of Load Power Supply Portable Instruments Distributed Power Systems Battery-Powered Equipment
TYPICAL APPLICATION
High Efficiency 1MHz, 5A Step-Down Regulator
VIN 4V TO 15V 22F 2
Efficiency and Power Loss
100 VIN = 12V 90 f = 1MHz 80 EFFICIENCY (%) 70 60 50 40 30 20 10 PGND 0 10 100 1000 OUTPUT CURRENT (mA) 0.1 10000
3605 TA01b
VOUT = 3.3V
10
PVIN CLKOUT CLKIN
SVIN INTVCC
POWER LOSS (W)
2.2F 0.1F
VOUT = 1.2V
1
BOOST PGOOD LTC3605 SW VON VIN RUN RT FB ITH
L 11.5k 2.55k 47F 2
VOUT 3.3V
VOUT = 3.3V
VOUT = 1.2V
0
16k 162k 220pF
3605 TA01a
3605fa
1
LTC3605 ABSOLUTE MAXIMUM RATINGS
(Note 1)
PIN CONFIGURATION
TOP VIEW CLKOUT INTVCC BOOST CLKIN SGND SVIN 18 PVIN 17 PVIN 25 16 SW 15 SW 14 SW 13 SW 7 RUN 8 PGOOD 9 10 11 12 VON PGND SW SW
PVIN, SVIN, SW Voltage .............................. -0.3V to 15V PVIN, SW Transient Voltage ........................ -2V to 17.5V BOOST Voltage .......................... -0.3V to PVIN + INTVCC RUN Voltage ............................................. -0.3V to SVIN VON Voltage ............................................... -0.3V to SVIN INTVCC Voltage.......................................... -0.3V to 3.6V ITH, RT, CLKOUT, PGOOD Voltage ......... -0.3V to INTVCC CLKIN, PHMODE, MODE Voltage .......... -0.3V to INTVCC TRACK/SS, FB Voltage .......................... -0.3V to INTVCC Operating Temperature Range (Note 2)....-40C to 85C Junction Temperature (Note 5) ............................. 125C Storage Temperature Range...................-65C to 125C
24 23 22 21 20 19 RT 1 PHMODE 2 MODE 3 FB 4 TRACK/SS 5 ITH 6
UF PACKAGE 24-LEAD (4mm 4mm) PLASTIC QFN TJMAX = 125C, JA = 37C/W EXPOSED PAD (PIN 25) IS PGND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH LTC3605EUF#PBF TAPE AND REEL LTC3605EUF#TRPBF PART MARKING 3605 PACKAGE DESCRIPTION 24-Lead (4mm x 4mm) Plastic QFN TEMPERATURE RANGE -40C to 85C
Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3605fa
2
LTC3605 ELECTRICAL CHARACTERISTICS
SYMBOL PVIN IQ PARAMETER VIN Supply Range Input DC Supply Current Active Shutdown Feedback Reference Voltage Feedback Voltage Line Regulation Feedback Voltage Load Regulation Feedback Pin Input Current Error Amplifier Transconductance Minimum On-Time Minimum Off-Time Positive Inductor Valley Current Limit Top Power NMOS On-Resistance Bottom Power NMOS On-Resistance INTVCC Undervoltage Lockout Threshold Run Threshold 2 (IQ = 2mA) Run Threshold 1 (IQ = 400A) Internal VCC Voltage INTVCC Load Regulation Output Overvoltage PGOOD Upper Threshold Output Undervoltage PGOOD Lower Threshold PGOOD Hysteresis PGOOD Pull-Down Resistance PGOOD Leakage TRACK Pull-Up Current Oscillator Frequency CLKIN Threshold RT = 162k
l
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C.
CONDITIONS (Note 3) Mode = 0, RT = 162k VIN =12V, RUN = 0 ITH =1.2V (Note 4) -40C to 85C -40C to 125C VIN = 4V to 15V ITH = 1.2V ITH = 0.8V to 1.6V
l l l l
MIN 4
TYP
MAX 15
UNITS V mA A V V %/V % nA mS ns ns
2 11 0.594 0.592 0.600 0.600 0.001 0.1
5 40 0.606 0.608 0.02 0.2 30
VFB VFB(LINE) VFB(LOAD) IFB gm (EA) tON(MIN) tOFF(MIN) ILIM RTOP RBOTTOM VUVLO VRUN VINTVCC VINTVCC OV UV VFB(HYS) RPGOOD IPGOOD ITRACK/SS fOSC CLKIN
ITH = 1.2V
1.15
1.35 40 70
1.6
VFB = 0.57V INTVCC = 3.3V INTVCC = 3.3V INTVCC Falling INTVCC Hysteresis (Rising) RUN Rising RUN Rising 4V < VIN < 15V ILOAD = 0mA to 20mA VFB Rising VFB Falling VFB Returning 1mA Load 0.54V < VFB < 0.66V
5
6 70 35
7.5 150 55 2.8 1.3 0.75 3.4 13 -7
A m m V V V V V % % % %
2.4 1.2 0.45 3.2 7 -13
2.6 0.25 1.25 0.6 3.3 0.5 10 -10 1.5 12 2.5
25 2 4 1.2
A A MHz V
0.85
1 0.7
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LTC3605E is guaranteed to meet performance specifications from 0C to 85C. Specifications over the -40C to 85C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: Dynamic supply current is higher due to the internal gate charge being delivered at the switching frequency.
Note 4: The LTC3605 is tested in a feedback loop that adjusts VFB to achieve a specified error amplifier output voltage (ITH). Note 5: TJ is calculated from the ambient temperature TA and power dissipation as follows: TJ = TA + PD * (37C/W). See Thermal Considerations section. Note 6: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125C when overtemperature protection is active Continuous operation above the specified maximum operating junction temperature may impair device reliability.
3605fa
3
LTC3605 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25C unless otherwise specified.
Quiescent Current vs VIN
2.18 2.16 QUIESCENT CURRENT (mA) 2.14 2.12 2.10 2.08 2.06 2.04 2.02 2.00 0 3 6 9 VIN (V) 12 15
3605 G01
Shutdown Current vs VIN
14 13 SHUTDOWN CURRENT (A) 20 12 IINTVCC (mA) 11 10 9 8 7 6 0 0 3 6 9 VIN (V) 12 15
3605 G02
IINTVCC Current vs Frequency
25 MODE = 3.3V NO LOAD
MODE = 0V NO LOAD
15
10
5
0
0.5
1
1.5 2 2.5 3 3.5 FREQUENCY (MHz)
4
4.5
3605 G03
RDS(ON) vs Temperature
120 100 TOP FET RDS(ON) (m) 80 60 BOTTOM FET 40 20 0 -45 -20 NORMALIZED (%) 0.5 0 -0.5 -1.0 -1.5 1.5 1.0
Load Regulation
INTERNAL ITH COMPENSATION (ITH = 3.3V) VIN = 12V VOUT = 1.2V f = 1MHz MODE = INTVCC VOUT 50mV/DIV AC COUPLED IOUT 5A/DIV
Load Step (External ITH Compensation)
EXTERNAL ITH COMPENSATION
IL 5A/DIV VIN = 12V VOUT = 1.2V IOUT = 0A TO 5A 20s/DIV
3605 G06
5
30 55 80 105 130 TEMPERATURE (C)
3605 G04
0
1
2
4 3 IOUT (A)
5
6
7
3605 G05
Load Step (Internal ITH Compensation)
Output Tracking
4.5 4.0
Switching Frequency vs RT
FREQUENCY (MHz)
VOUT 50mV/DIV AC COUPLED
3.5 VTRACK VFB 3.0 2.5 2.0 1.5 1.0 VIN = 12V VOUT = 1.2V 500s/DIV
3605 G08
IOUT 5A/DIV VIN = 12V VOUT = 3.3V ITH = 3.3V IOUT = 0A TO 5A 20s/DIV
3605 G07
0.5 0 0 50 100 150 200 250 300 350 400 450 500 RT (k)
3605 G09
3605fa
4
LTC3605 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25C unless otherwise specified.
Switch Leakage vs VIN
350 300 SWITCH LEAKAGE (nA) 250 200 150 100 50 TOP SWITCH 0 0 4 8 12 VIN (V)
3605 G10
Efficiency vs VIN
98 96 ILOAD = 1A FREQUENCY (MHz) EFFICIENCY (%) VOUT = 3.3V 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 3 6 9 VIN (V) 12 15
3605 G11
Frequency vs VON Voltage
VIN = 14V RT = 162k
BOTTOM SWITCH
94 92 90 88 86 84 16 20 ILOAD = 5A
0 0 2 4 8 6 VON (V) 10 12 14
3605 G12
Current Limit Foldback
NORMALIZED MAXIMUM OUTPUT CURRENT (%) 120 100 NORMALIZED INTVCC (%) 80 60 40 20 0 0 0.1 0.2 0.3 0.4 VFB (V) 0.5 0.6 0.7 101 100 99 98 97 96 95 94 93 92 91 90
INTVCC Load Regulation
TA = 25C 1.30 1.25 RUN THRESHOLD (V) 1.20 1.15 1.10 1.05
RUN Pin Threshold vs Temperature
0
80 100 120 60 40 20 INTVCC OUTPUT CURRENT (mA)
140
1.00 -40
-15
60 35 85 10 TEMPERATURE (C)
110
3605 G15
3605 G13
3605 G14
DCM Operation
CLKOUT 2V/DIV CLKOUT 2V/DIV
CCM Operation
VSW 5V/DIV IL 2A/DIV
VSW 5V/DIV
IL 2A/DIV VIN = 12V VOUT = 1.2V MODE = 0 IOUT = 0 L1 = 0.33H 400ns/DIV
3605 G16
VIN = 12V 400ns/DIV VOUT = 1.2V MODE = 3.3V PHMODE = 3.3V IOUT = 0 L1 = 0.33H
3605 G17
3605fa
5
LTC3605 PIN FUNCTIONS
RT (Pin 1): Oscillator Frequency Programming Pin. Connect an external resistor (between 200k to 40k) from RT to SGND to program the frequency from 800kHz to 4MHz. Since the synchronization range is 30% of set frequency, be sure that the set frequency is within this percentage range of the external clock to ensure frequency lock. PHMODE (Pin 2): Control Input to Phase Selector. Determines the phase relationship between internal oscillator and CLKOUT. Tie it to INTVCC for 2-phase operation, tie it to SGND for 3-phase operation, and tie it to INTVCC/2 for 4-phase operation. MODE (Pin 3): Operation Mode Select. Tie this pin to INTVCC to force continuous synchronous operation at all output loads. Tying it to SGND enables discontinuous mode operation at light loads. Tying this pin to INTVCC /2 shuts off the internal clock during discontinuous intervals. FB (Pin 4): Output Feedback Voltage. Input to the error amplifier that compares the feedback voltage to the internal 0.6V reference voltage. This pin is normally connected to a resistive divider from the output voltage. TRACK/SS (Pin 5): Output Tracking and Soft-Start Pin. Allows the user to control the rise time of the output voltage. Putting a voltage below 0.6V on this pin bypasses the internal reference input to the error amplifier, instead it servos the FB pin to the TRACK voltage. Above 0.6V, the tracking function stops and the internal reference resumes control of the error amplifier. There's an internal 2A pull-up current from INTVCC on this pin, so putting a capacitor here provides soft-start function. ITH (Pin 6): Error Amplifier Output and Switching Regulator Compensation Point. The current comparator's trip threshold is linearly proportional to this voltage, whose normal range is from 0.3V to 1.8V. Tying this pin to INTVCC activates internal compensation and output voltage positioning, raising VOUT to 1.5% higher than the nominal value at IOUT = 0 and 1.5% lower at IOUT = 5A. RUN (Pin 7): Run Control Input. Enables chip operation by tying RUN above 1.2V. Tying it below 1.1V shuts down the part. PGOOD (Pin 8): Output Power Good with Open-Drain Logic. PGOOD is pulled to ground when the voltage on the FB pin is not within 10% of the internal 0.6V reference. VON (Pin 9): On-Time Voltage Input. Voltage trip point for the on-time comparator. Tying this pin to the output voltage makes the on-time proportional to VOUT and keeps the switching frequency constant at different VOUT. However, when VON is <0.6V or >6V, then switching frequency will no longer remain constant. PGND (Pin 10): Power Ground. SW (Pins 11 to 16): Switch Node Connection to External Inductor. Voltage swing of SW is from a diode voltage drop below ground to PVIN. PVIN (Pins 17, 18): Power VIN. Input voltage to the onchip power MOSFETs. SVIN (Pin 19): Signal VIN. Filtered input voltage to the on-chip 3.3V regulator. Connect a (1 to 10) resistor between SVIN and PVIN and bypass to GND with a 0.1F capacitor. BOOST (Pin 20): Boosted Floating Driver Supply for Internal Top Power MOSFET. The (+) terminal of the bootstrap capacitor connects here. This pin swings from a diode voltage drop below INTVCC up to PVIN + INTVCC. INTVCC (Pin 21): Internal 3.3V Regulator Output. The internal power drivers and control circuits are powered from this voltage. Decouple this pin to power ground with a minimum of 1F low ESR ceramic capacitor. SGND (Pin 22): Signal Ground Connection. CLKOUT (Pin 23): Output Clock Signal for PolyPhase Operation. The phase of CLKOUT with respect to CLKIN is determined by the state of the PHMODE pin. CLKOUT's peak-to-peak amplitude is INTVCC to GND. CLKIN (Pin 24): External Synchronization Input to Phase Detector. This pin is internally terminated to SGND with 20k. The phase-locked loop will force the top power NMOS's turn on signal to be synchronized with the rising edge of the CLKIN signal. Exposed Pad (Pin 25): Power Ground on Bottom Exposed Pad. Return path of internal power MOSFETs. Connect this pin to the negative terminals of the input capacitor and output capacitor.
3605fa
6
LTC3605 BLOCK DIAGRAM
VOUT VON 9 100K 35pF 3pF 0.6V 6V 3.3V REG SVIN 19 CIN2 3 MODE CIN 17-18 1 PVIN
ION PLL-SYNC (50%)
ION OST V tON = VON (0.64pF) IION R S INTVCC 21
x=
VIN INTVCC
Q
BOOST 20 TG CB M1
12 x OSC RT 1 RT CLKIN 24 PHMODE 2 OSC PLL-SYNC (30%) 20k ON SW SWITCH LOGIC AND ANTISHOOT THROUGH RUN CLKOUT 23 100k 35pF 3.3A -3.3A TO 6.7A 3pF FOLDBACK DISABLED AT START-UP OV 11-16 SENSE+ SENSE- DB
+
ICMP
+
IREV
L1 VOUT
-
-
COUT BG CVCC PGND 10, 25 8 PGOOD R2 M2
0A TO 10A
+
FOLDBACK x 4 + 0.6
0.3V
1 180k Q2 Q4 ITHB Q6
- -
OV 0.66V FB
+
4
Q1 UV
R1
- +
SS EA RUN INTVCC 0.54V
SGND 22
0.6V
1.2V
0.6V REF 6
ITH RC CC1 7
+
RUN 5
-
+
-
2A
-++
TRACK/SS CSS
3605 BD
3605fa
7
LTC3605 OPERATION
Main Control Loop The LTC3605 is a current mode monolithic step-down regulator. In normal operation, the internal top power MOSFET is turned on for a fixed interval determined by a one-shot timer, OST. When the top power MOSFET turns off, the bottom power MOSFET turns on until the current comparator, ICMP , trips, restarting the one-shot timer and initiating the next cycle. Inductor current is determined by sensing the voltage drop across the bottom power MOSFET 's VDS. The voltage on the ITH pin sets the comparator threshold corresponding to the inductor valley current. The error amplifier, EA, adjusts this ITH voltage by comparing the feedback signal, VFB, from the output voltage with that of an internal 0.6V reference. If the load current increases, it causes a drop in the feedback voltage relative to the internal reference. The ITH voltage then rises until the average inductor current matches that of the load current. At low load current, the inductor current can drop to zero and become negative. This is detected by current reversal comparator, IREV , which then shuts off the bottom power MOSFET, resulting in discontinuous operation. Both power MOSFETs will remain off with the output capacitor supplying the load current until the ITH voltage rises above the zero current level (0.6V) to initiate another cycle. Discontinuous mode operation is disabled by tying the MODE pin to INTVCC, which forces continuous synchronous operation regardless of output load. The operating frequency is determined by the value of the RT resistor, which programs the current for the internal oscillator. An internal phase-lock loop servos the oscillator frequency to an external clock signal if one is present on the CLKIN pin. Another internal phase-lock loop servos the switching regulator on-time to track the internal oscillator to force constant switching frequency. Overvoltage and undervoltage comparators OV and UV pull the PGOOD output low if the output feedback voltage, VFB, exits a 10% window around the regulation point. Continuous operation is forced during OV and UV condition except during start-up when the TRACK pin is ramping up to 0.6V. Foldback current limiting is provided if the output is shorted to ground. As VFB drops to zero, the maximum sense voltage allowed across the bottom power MOSFET is lowered to approximately 40% of the original value to reduce the inductor valley current. Pulling the RUN pin to ground forces the LTC3605 into its shutdown state, turning off both power MOSFETs and most of its internal control circuitry. Bringing the RUN pin above 0.7V turns on the internal reference only, while still keeping the power MOSFETs off. Further increasing the RUN voltage above 1.2V turns on the entire chip. INTVCC Regulator An internal low dropout (LDO) regulator produces the 3.3V supply that powers the drivers and the internal bias circuitry. The INTVCC can supply up to 100mA RMS and must be bypassed to ground with a minimum of 1F ceramic capacitor. Good bypassing is necessary to supply the high transient currents required by the power MOSFET gate drivers. Applications with high input voltage and high switching frequency will increase die temperature because of the higher power dissipation across the LDO. Connecting a load to the INTVCC pin is not recommended since it will further push the LDO into its RMS current rating while increasing power dissipation and die temperature. VIN Overvoltage Protection In order to protect the internal power MOSFET devices against transient voltage spikes, the LTC3605 constantly monitors the VIN pin for an overvoltage condition. When VIN rises above 17V, the regulator suspends operation by shutting off both power MOSFETs. Once VIN drops below 15V, the regulator immediately resumes normal operation. The regulator does not execute its soft-start function when exiting an overvoltage condition.
3605fa
8
LTC3605 OPERATION
Output Voltage Programming The output voltage is set by an external resistive divider according to the following equation: VOUT = 0.6V * (1 + R2/R1) The resistive divider allows the VFB pin to sense a fraction of the output voltage as shown in Figure 1.
VOUT R2 FB LTC3605 SGND
3605 F01
Output Power Good When the LTC3605's output voltage is within the 10% window of the regulation point, which is reflected back as a VFB voltage in the range of 0.54V to 0.66V, the output voltage is good and the PGOOD pin is pulled high with an external resistor. Otherwise, an internal open-drain pulldown device (12) will pull the PGOOD pin low. To prevent unwanted PGOOD glitches during transients or dynamic VOUT changes, the LTC3605's PGOOD falling edge includes a blanking delay of approximately 52 switching cycles. Multiphase Operation For output loads that demand more than 5A of current, multiple LTC3605s can be cascaded to run out of phase to provide more output current. The CLKIN pin allows the LTC3605 to synchronize to an external clock (50% of frequency programmed by RT) and the internal phaselocked-loop allows the LTC3605 to lock onto CLKIN's phase as well. The CLKOUT signal can be connected to the CLKIN pin of the following LTC3605 stage to line up both the frequency and the phase of the entire system. Tying the PHMODE pin to INTVCC, SGND or INTVCC/2 generates a phase difference (between CLKIN and CLKOUT) of 180 degrees, 120 degrees, or 90 degrees respectively, which corresponds to 2-phase, 3-phase or 4-phase operation. A total of 12 phases can be cascaded to run simultaneously out of phase with respect to each other by programming the PHMODE pin of each LTC3605 to different levels. Internal/External ITH Compensation During single phase operation, the user can simplify the loop compensation by tying the ITH pin to INTVCC to enable internal compensation. This connects an internal 30k resistor in series with a 40pF capacitor to the output of the error amplifier (internal ITH compensation point) while also activating output voltage positioning such that the output voltage will be 1.5% above regulation at no load and 1.5% below regulation at full load. This is a trade-off for simplicity instead of OPTI-LOOP(R) optimization, where ITH components are external and are selected to optimize the loop transient response with minimum output capacitance.
OPTI-LOOP is a registered trademark of Linear Technology Corporation.
3605fa
CFF
R1
Figure 1. Setting the Output Voltage
Programming Switching Frequency Connecting a resistor from the RT pin to SGND programs the switching frequency from 800kHz to 4MHz according to the following formula: Frequency (Hz) = 1.6e11 R T ()
The internal PLL has a synchronization range of 30% around its programmed frequency. Therefore, during external clock synchronization be sure that the external clock frequency is within this 30% range of the RT programmed frequency. Output Voltage Tracking and Soft-Start The LTC3605 allows the user to program its output voltage ramp rate by means of the TRACK/SS pin. An internal 2A pulls up the TRACK/SS pin to INTVCC. Putting an external capacitor on TRACK/SS enables soft starting the output to prevent current surge on the input supply. For output tracking applications, TRACK/SS can be externally driven by another voltage source. From 0V to 0.6V, the TRACK/SS voltage will override the internal 0.6V reference input to the error amplifier, thus regulating the feedback voltage to that of TRACK/SS pins. When TRACK/SS is above 0.6V, tracking is disabled and the feedback voltage will regulate to the internal reference voltage.
9
LTC3605 OPERATION
Minimum Off-Time and Minimum On-Time Considerations The minimum off-time, tOFF(MIN), is the smallest amount of time that the LTC3605 is capable of turning on the bottom power MOSFET, tripping the current comparator and turning the power MOSFET back off. This time is generally about 70ns. The minimum off-time limit imposes a maximum duty cycle of tON/(tON + tOFF(MIN)). If the maximum duty cycle is reached, due to a dropping input voltage for example, then the output will drop out of regulation. The minimum input voltage to avoid dropout is: VIN(MIN) = VOUT * tON + tOFF(MIN) tON IRMS IOUT(MAX) VOUT VIN VIN -1 VOUT
This formula has a maximum at VIN = 2VOUT, where IRMS IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. For low input voltage applications, sufficient bulk input capacitance is needed to minimize transient effects during output load changes. The selection of COUT is determined by the effective series resistance (ESR) that is required to minimize voltage ripple and load step transients as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. Loop stability can be checked by viewing the load transient response. The output ripple, VOUT, is determined by: 1 VOUT < IL + ESR 8 * f * COUT The output ripple is highest at maximum input voltage since IL increases with input voltage. Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirements. Dry tantalum, special polymer, aluminum electrolytic, and ceramic capacitors are all available in surface mount packages. Special polymer capacitors are very low ESR but have lower capacitance density than other types. Tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. Aluminum electrolytic capacitors have significantly higher ESR, but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long-term reliability. Ceramic capacitors have excellent low ESR characteristics and small footprints. Their relatively low value of bulk capacitance may require multiples in parallel.
3605fa
Conversely, the minimum on-time is the smallest duration of time in which the top power MOSFET can be in its "on" state. This time is typically 40ns. In continuous mode operation, the minimum on-time limit imposes a minimum duty cycle of: DCMIN = f * tON(MIN) where tON(MIN) is the minimum on-time. As the equation shows, reducing the operating frequency will alleviate the minimum duty cycle constraint. In the rare cases where the minimum duty cycle is surpassed, the output voltage will still remain in regulation, but the switching frequency will decrease from its programmed value. This is an acceptable result in many applications, so this constraint may not be of critical importance in most cases. High switching frequencies may be used in the design without any fear of severe consequences. As the sections on inductor and capacitor selection show, high switching frequencies allow the use of smaller board components, thus reducing the size of the application circuit. CIN and COUT Selection The input capacitance, CIN, is needed to filter the trapezoidal wave current at the drain of the top power MOSFET. To prevent large voltage transients from occurring, a low ESR input capacitor sized for the maximum RMS current should be used. The maximum RMS current is given by:
10
LTC3605 OPERATION
Using Ceramic Input and Output Capacitors Higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. Their high ripple current, high voltage rating and low ESR make them ideal for switching regulator applications. However, care must be taken when these capacitors are used at the input and output. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the VIN input. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at VIN large enough to damage the part. When choosing the input and output ceramic capacitors, choose the X5R and X7R dielectric formulations. These dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size. Since the ESR of a ceramic capacitor is so low, the input and output capacitor must instead fulfill a charge storage requirement. During a load step, the output capacitor must instantaneously supply the current to support the load until the feedback loop raises the switch current enough to support the load. The time required for the feedback loop to respond is dependent on the compensation and the output capacitor size. Typically, 3 to 4 cycles are required to respond to a load step, but only in the first cycle does the output drop linearly. The output droop, VDROOP , is usually about 2 to 3 times the linear drop of the first cycle. Thus, a good place to start with the output capacitor value is approximately: COUT 2.5 IOUT fO * VDROOP Inductor Selection Given the desired input and output voltages, the inductor value and operating frequency determine the ripple current: IL = VOUT V 1- OUT f * L VIN(MAX)
Lower ripple current reduces core losses in the inductor, ESR losses in the output capacitors and output voltage ripple. Highest efficiency operation is obtained at low frequency with small ripple current. However, achieving this requires a large inductor. There is a trade-off between component size, efficiency and operating frequency. A reasonable starting point is to choose a ripple current that is about 50% of IOUT(MAX). This is especially important at low VOUT operation where VOUT is 1.8V or below. Care must be given to choose an inductance value that will generate a big enough current ripple (40% to 50%) so that the chip's valley current comparator has enough signal-to-noise ratio to force constant switching frequency. Meanwhile, also note that the largest ripple current occurs at the highest VIN. To guarantee that ripple current does not exceed a specified maximum, the inductance should be chosen according to: L= VOUT V * 1- OUT f * IL(MAX) VIN(MAX)
More capacitance may be required depending on the duty cycle and load step requirements. In most applications, the input capacitor is merely required to supply high frequency bypassing, since the impedance to the supply is very low. A 22F ceramic capacitor is usually enough for these conditions. Place this input capacitor as close to the PVIN pins as possible.
Once the value for L is known, the type of inductor must be selected. Actual core loss is independent of core size for a fixed inductor value, but is very dependent on the inductance selected. As the inductance or frequency increases, core losses decrease. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates "hard", which means that
3605fa
11
LTC3605 OPERATION
inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate!
Table 1. Inductor Selection Table
INDUCTANCE 0.33H 0.47H 0.68H 0.82H 1.0H 0.22H 0.47H 0.20H 0.47H 1H 0.47H 0.75H 1H 0.22H 0.47H 0.68H 0.82H 1H 1.5H 1H 1.5H 2.2H 0.25H 0.47H 0.72H 1H 1.5H DCR 4.1m 6.5m 9.4m 11.8m 14.2m 4.1m 15m 4.5m 8.3m 18.3m 4.5m 7.5m 9m 2.8m 4.2m 5.5m 8m 10m 14m 8.8m 9.6m 12m 2.5m 3.4m 7.5m 9.5m 10.5m MAX CURRENT 18A 13.5A 11A 10A 9A 12A 7A 12.4A 9A 5.7A 16.6A 12.2A 10.6A 23A 17A 15A 13A 11A 9A 6.4A 6.1A 5.4A 18A 16A 12A 11A 9A 7mm x 7.7mm 3.8mm 6.9mm x 7.3mm 3.2mm 7mm x 7.3mm 3.0mm 6.9mm x 7.7mm 3.0mm 7mm x 7.7mm 2.0mm 4.3mm x 4.7mm 2.0mm DIMENSIONS 6.7mm x 7mm HEIGHT 3mm Vishay IHLP-2525CZ-01 Series
Different core materials and shapes will change the size/current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are small and don't radiate much energy, but generally cost more than powdered iron core inductors with similar characteristics. The choice of which style inductor to use mainly depends on the price versus size requirements and any radiated field/EMI requirements. New designs for surface mount inductors are available from Toko, Vishay, NEC/Tokin, Cooper, TDK and Wurth Electronik. Refer to Table 1 for more details. Checking Transient Response The OPTI-LOOP compensation allows the transient response to be optimized for a wide range of loads and output capacitors. The availability of the ITH pin not only allows optimization of the control loop behavior but also provides a DC coupled and AC filtered closed-loop response test point. The DC step, rise time and settling at this test point truly reflects the closed-loop response. Assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. The ITH external components shown in the circuit on the first page of this data sheet provides an adequate starting point for most applications. The series R-C filter sets the dominant pole zero loop compensation. The values can be modified slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the final PC layout is done and the particular output capacitor type and value have been determined. The output capacitors need to be selected because their various types and values determine the loop feedback factor gain and phase. An output current pulse of 20% to 100% of full load current having a rise time of 1s to 10s will produce output voltage and ITH pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to ILOAD * ESR, where ESR is the effective series resistance of COUT. ILOAD also begins to charge or discharge COUT generating a feedback error signal used by the regulator to return VOUT to its
3605fa
Vishay IHLP-1616BZ-11 Series
Toko FDV0620 Series
NEC/Tokin MLC0730L Series
Cooper HCP0703 Series
TDK RLF7030 Series
Wurth Electronik WE-HC 744312 Series
12
LTC3605 OPERATION
steady-state value. During this recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability problem. The initial output voltage step may not be within the bandwidth of the feedback loop, so the standard second order overshoot/DC ratio cannot be used to determine phase margin. The gain of the loop increases with the R and the bandwidth of the loop increases with decreasing C. If R is increased by the same factor that C is decreased, the zero frequency will be kept the same, thereby keeping the phase the same in the most critical frequency range of the feedback loop. In addition, a feedforward capacitor, CFF , can be added to improve the high frequency response, as shown in Figure 1. Capacitor CFF provides phase lead by creating a high frequency zero with R2 which improves the phase margin. The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. For a detailed explanation of optimizing the compensation components, including a review of control loop theory, refer to Linear Technology Application Note 76. In some applications, a more severe transient can be caused by switching in loads with large (>10F) input capacitors. The discharged input capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can deliver enough current to prevent this problem, if the switch connecting the load has low resistance and is driven quickly. The solution is to limit the turn-on speed of the load switch driver. A Hot SwapTM controller is designed specifically for this purpose and usually incorporates current limiting, short-circuit protection and soft-starting. Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: % Efficiency = 100%-(L1 + L2 + L3 +...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, three main sources usually account for most of the losses in LTC3605 circuits: 1) I2R losses, 2) switching and biasing losses, 3) other losses. 1. I2R losses are calculated from the DC resistances of the internal switches, RSW, and external inductor, RL. In continuous mode, the average output current flows through inductor L but is "chopped" between the internal top and bottom power MOSFETs. Thus, the series resistance looking into the SW pin is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (DC) as follows: RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1-DC) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics curves. Thus to obtain I2R losses: I2R losses = IOUT2(RSW + RL) 2. The INTVCC current is the sum of the power MOSFET driver and control currents. The power MOSFET driver current results from switching the gate capacitance of the power MOSFETs. Each time a power MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from INTVCC to ground. The resulting dQ/dt is a current out of INTVCC that is typically much larger than the DC control bias current. In continuous mode, IGATECHG = f(QT + QB), where QT and QB are the gate charges of the internal top and bottom power MOSFETs and f is the switching frequency. Since INTVCC is a low dropout regulator output powered by VIN, its power loss equals: PLDO = VIN * IINTVCC Refer to the IINTVCC vs Frequency curve in the Typical Performance Characterics for typical INTVCC current at various frequencies. 3. Other "hidden" losses such as transition loss and copper trace and internal load resistances can account for additional efficiency degradations in the overall power
Hot Swap is a trademark of Linear Technology Corporation.
3605fa
13
LTC3605 OPERATION
system. It is very important to include these "system" level losses in the design of a system. Transition loss arises from the brief amount of time the top power MOSFET spends in the saturated region during switch node transitions. The LTC3605 internal power devices switch quickly enough that these losses are not significant compared to other sources. Other losses including diode conduction losses during dead-time and inductor core losses which generally account for less than 2% total additional loss. Thermal Considerations In a majority of applications, the LTC3605 does not dissipate much heat due to its high efficiency and low thermal resistance of its exposed-back QFN package. However, in applications where the LTC3605 is running at high ambient temperature, high VIN, high switching frequency and maximum output current load, the heat dissipated may exceed the maximum junction temperature of the part. If the junction temperature reaches approximately 160C, both power switches will be turned off until the temperature drops about 15C cooler. To avoid the LTC3605 from exceeding the maximum junction temperature, the user will need to do some thermal analysis. The goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. The temperature rise is given by: TRISE = PD * JA As an example, consider the case when the LTC3605 is used in applications where VIN = 12V, IOUT = 5A, f = 1MHz, VOUT = 1.8V. The equivalent power MOSFET resistance RSW is: RSW = RDS(ON)Top * = 70m * V VOUT + RDS(ON)Bot 1- OUT VIN VIN and internal biasing current loss, transition loss, inductor core loss and other losses in the application. Therefore, the total power dissipated by the part is: PD = IOUT2 * RSW + VIN * IVIN (No Load) = 25A * 40.25m + 12V * 11mA = 1.14W The QFN 4mm x 4mm package junction-to-ambient thermal resistance, JA, is around 37C/W. Therefore, the junction temperature of the regulator operating in a 25C ambient temperature is approximately: TJ = 1.14 * 37 + 25 = 67C Remembering that the above junction temperature is obtained from an RDS(ON) at 25C, we might recalculate the junction temperature based on a higher RDS(ON) since it increases with temperature. Redoing the calculation assuming that RSW increased 15% at 67C yields a new junction temperature of 72C. If the application calls for a higher ambient temperature and/or higher switching frequency, care should be taken to reduce the temperature rise of the part by using a heat sink or air flow. Figure 2 is a temperature derating curve based on the DC1215 demo board.
6 5 LOAD CURRENT (A) 4 3 2 1 0 VIN = 12V VOUT = 3.3V fSW = 1MHz DC1215 DEMO BOARD 20 120 60 80 100 40 AMBIENT TEMPERATURE (C) 140
3605 F02
Figure 2. Load Current vs Ambient Temperature
1.8 10.2 + 35m * 12 12 = 40.25m
Junction Temperature Measurement The junction-to-ambient thermal resistance will vary depending on the size and amount of heat sinking copper on the PCB board where the part is mounted, as well as the amount of air flow on the device. One of the ways to
3605fa
The VIN current during 1MHz force continuous operation with no load is about 11mA, which includes switching
14
LTC3605 OPERATION
measure the junction temperature directly is to use the internal junction diode on one of the pins (PGOOD) to measure its diode voltage change based on ambient temperature change. First remove any external passive component on the PGOOD pin, then pull out 100A from the PGOOD pin to turn on its internal junction diode and bias the PGOOD pin to a negative voltage. With no output current load, measure the PGOOD voltage at an ambient temperature of 25C, 75C and 125C to establish a slope relationship between the delta voltage on PGOOD and delta ambient temperature. Once this slope is established, then the junction temperature rise can be measured as a function of power loss in the package with corresponding output load current. Keep in mind that doing so will violate absolute maximum voltage ratings on the PGOOD pin, however, with the limited current, no damage will result. Board Layout Considerations When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3605 (refer to Figure 3). Check the following in your layout: 1. Do the capacitors CIN connect to the power PVIN and power PGND as close as possible? These capacitors provide the AC current to the internal power MOSFETs and their drivers. 2. Are COUT and L1 closely connected? The (-) plate of COUT returns current to PGND and the (-) plate of CIN. 3. The resistive divider, R1 and R2, must be connected between the (+) plate of COUT and a ground line terminated near SGND. The feedback signal VFB should be routed away from noisy components and traces, such as the SW line, and its trace should be minimized. Keep R1 and R2 close to the IC. 4. Solder the Exposed Pad (Pin 25) on the bottom of the package to the PGND plane. Connect this PGND plane to other layers with thermal vias to help dissipate heat from the LTC3605. 5. Keep sensitive components away from the SW pin. The RT resistor, the compensation capacitor CC and CITH and all the resistors R1, R3 and RC, and the INTVCC bypass capacitor, should be placed away from the SW trace and the inductor L1. Also, the SW pin pad should be kept as small as possible. 6. A ground plane is preferred, but if not available, keep the signal and power grounds segregated with smallsignal components returning to the SGND pin which is then connected to the PGND pin at the negative terminal of the output capacitor, COUT. Flood all unused areas on all layers with copper, which reduces the temperature rise of power components. These copper areas should be connected to PGND.
CIN
L1
GND
VIN
VOUT COUT
VIN
VOUT
GND
Figure 3a. Sample PCB Layout--Topside
Figure 3b. Sample PCB Layout--Bottom Side
3605fa
15
LTC3605 OPERATION
Design Example As a design example, consider using the LTC3605 in an application with the following specifications: VIN = 10.8V to 13.2V, VOUT = 1.8V, IOUT(MAX) = 5A, IOUT(MIN) = 500mA, f = 2MHz Because efficiency is important at both high and low load current, discontinuous mode operation will be utilized. First select from the characteristic curves the correct RT resistor value for 2MHz switching frequency. Based on that RT should be 80.6k. Then calculate the inductor value for about 50% ripple current at maximum VIN: 1.8V 1.8V L= 1- 13.2V = 0.31H 2MHz * 2.5A The nearest standard value inductor would be 0.33H. COUT will be selected based on the ESR that is required to satisfy the output voltage ripple requirement and the bulk capacitance needed for loop stability. For this design, two 47F ceramic capacitors will be used. CIN should be sized for a maximum current rating of: 1.8V 13.2V IRMS = 5A - 1 13.2V 1.8V
1/ 2
= 1.7A
Decoupling the PVIN pins with two 22F ceramic capacitors is adequate for most applications.
TYPICAL APPLICATIONS
12V to 1.2V 4MHz Buck Regulator
C1 2.2F D1 0.1F 10 24 1 2 3 4 5 16.2k 220pF 10pF 6 0.1F 23 22 21 20 19 18 17 16 L1 0.2H 15 14 13 COUT 47F 2 4.99k VOUT 1.2V 5A CIN 22F 2 VIN 4V TO 15V
CLKIN CLKOUT SGND INTVCC BOOST SVIN RT PHMODE MODE LTC3605 FB TRACK/SS ITH RUN 7 SVIN PGOOD 8 100k PGND VON 9 PGND 10 SW 11 SW SW SW SW 12 PVIN PVIN SW
0.1F
40.2k
4.99k
SGND
3605 TA02
C1: AVX 0805ZD225MAT2A CIN: TDK C4532X5RIC226M COUT: TDK C3216X5ROJ476M
D1: CENTRAL SEMI CMDSH-3 L1: VISHAY IHLP-2525CZERR20-M01
3605fa
16
LTC3605 TYPICAL APPLICATIONS
12V, 10A 2-Phase Single Output Regulator
0.1F C1 2.2F
D1 10 VIN 4V TO 15V
24 1 2 3 4 5 6 16.2k 220pF 10pF 0.1F
23
22
21
20
19 18 17 16
CIN1 22F
CLKIN CLKOUT SGND INTVCC BOOST SVIN RT PHMODE MODE LTC3605 FB TRACK/SS ITH RUN 7 SVIN PGOOD 8 100k PGND VON 9 PGND 10 SW 11 SW SW SW SW 12 PVIN PVIN SW
0.1F
162k
L1 1H 15 14 13 COUT1 47F 22.6k
VOUT 3.3V 10A
4.99k
SGND
0.1F C2 2.2F
D2 10
24 1 2 3 4 5 6 16.2k 220pF 10pF
23
22
21
20
19 18 17 16
CLKIN CLKOUT SGND INTVCC BOOST SVIN RT PHMODE MODE LTC3605 FB TRACK/SS ITH RUN 7 SVIN PGND PGOOD 8 VON 9 PGND 10 SW 11 SW SW SW SW 12 PVIN PVIN SW
CIN2 22F 0.1F
162k
L2 1H 15 14 13 COUT2 47F
C1, C2: AVX 0805ZD225MAT2A CIN1, CIN2: TDK C4532X5RIC226M COUT1, COUT2: TDK C3216X5ROJ476M D1, D2: CENTRAL SEMI CMDSH-3 L1, L2: VISHAY IHLP-2525CZER1R0-M01
SGND
3605 TA03
3605fa
17
LTC3605 TYPICAL APPLICATIONS
Dual Output Tracking Application
C1 2.2F
D1
0.1F 10 VIN1 4V TO 15V
24 1 2 3 4 5 16.2k 100pF 10pF 6 0.1F
23
22
21
20
19 18 17 16
CLKIN CLKOUT SGND INTVCC BOOST SVIN RT PHMODE MODE LTC3605 FB TRACK/SS ITH RUN 7 SVIN1 PGOOD 8 100k PGND VON 9 PGND 10 SW 11 SW SW SW SW 12 PVIN PVIN SW
CIN1 22F 2
0.1F
162k
L1 0.33H 15 14 13 COUT1 47F 7.5k
VOUT1 1.8V 5A
2.49k
4.99k SGND
C2 2.2F
D2
0.1F 10 VIN2 4V TO 15V
24 1 2 3 4 5 16.2k 100pF 10pF 6
23
22
21
20
19 18 17 16
CLKIN CLKOUT SGND INTVCC BOOST SVIN RT PHMODE MODE LTC3605 FB TRACK/SS ITH RUN 7 SVIN2 PGOOD 8 100k PGND VON 9 PGND 10 SW 11 SW SW SW SW 12 PVIN PVIN SW
CIN2 22F 2
0.1F
162k
L2 0.33H 15 14 13 COUT2 47F
VOUT2 1.2V 5A 4.99k
4.99k
SGND
3605 TA04
C1, C2: AVX 0805ZD225MAT2A CIN1, CIN2: TDK C4532X5RIC226M COUT1, COUT2: TDK C3216X5ROJ476M D1, D2: CENTRAL SEMI CMDSH-3 L1, L2: VISHAY IHLP-2525CZERR33-M01
3605fa
18
LTC3605 PACKAGE DESCRIPTION
UF Package 24-Lead Plastic QFN (4mm x 4mm)
(Reference LTC DWG # 05-08-1697 Rev B)
0.70 0.05
4.50 0.05 2.45 0.05 3.10 0.05 (4 SIDES)
PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 0.75 0.05 BOTTOM VIEW--EXPOSED PAD R = 0.115 TYP PIN 1 NOTCH R = 0.20 TYP OR 0.35 x 45 CHAMFER
4.00 0.10 (4 SIDES) PIN 1 TOP MARK (NOTE 6)
23 24 0.40 0.10 1 2
2.45 0.10 (4-SIDES)
(UF24) QFN 0105
0.200 REF 0.00 - 0.05 NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)--TO BE APPROVED 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
0.25 0.05 0.50 BSC
3605fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC3605 TYPICAL APPLICATION
-3.6V Negative Converter
CIN 22F 2 VIN 3V TO 10V 0.1F D1 10 24 1 2 3 4 5 16.2k 470pF 47pF 6 0.1F 23 22 21 20 19 18 17 16 L1 1H 15 14 13 COUT 47F 2 24.9k
C1 2.2F
CLKIN CLKOUT SGND INTVCC BOOST SVIN RT PHMODE MODE LTC3605 FB TRACK/SS ITH RUN 7 SVIN PGOOD 8 100k VON 9 PGND 10 SW 11 SW SW SW SW 12 PVIN PVIN SW
0.1F
162k
4.99k
3605 TA05
VOUT -3.6V 2A
RELATED PARTS
PART NUMBER LTC3412A LTC3413 LTC3414/LTC3416 LTC3415 LTC3418 LTC3602 LTC3603 LTC3608 LTC3610 LTC3611 DESCRIPTION 3A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter COMMENTS 95% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.8V, IQ = 60A, ISD < 1A, TSSOP16E, 4mm x 4mm QFN16
3A (IOUT Sink/Source), 2MHz, Monolithic Synchronous Regulator 90% Efficiency, VIN: 2.25V to 5.5V, VREF/2, IQ = 280A, for DDR/QDR Memory Termination ISD < 1A, TSSOP16E 4A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converters 7A (IOUT), 1.5MHz, Synchronous Step-Down DC/DC Converter 8A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter 2.5A (IOUT), 3MHz, Synchronous Step-Down DC/DC Converter 2.5A (IOUT), 3MHz, Synchronous Step-Down DC/DC Converter 18V, 8A (IOUT) 1MHz, Synchronous Step-Down DC/DC Converter 24V, 12A (IOUT), 1MHz, Synchronous Step-Down DC/DC Converter 32V, 10A (IOUT), 1MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.8V, IQ = 64A, ISD < 1A, TSSOP20E 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 450A, ISD < 1A, 5mm x 7mm QFN38 95% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.8V, IQ = 380A, ISD < 1A, 5mm x 7mm QFN38 95% Efficiency, VIN: 4.5V to 10V, VOUT(MIN) = 0.6V, IQ = 75A, ISD < 1A, 4mm x 4mm QFN20, TSSOP16E 95% Efficiency, VIN: 4.5V to 15V, VOUT(MIN) = 0.6V, IQ = 75A, ISD < 1A, 3mm x 3mm QFN16, MSE16 95% Efficiency, VIN: 4V to 18V, VOUT(MIN) = 0.6V, IQ = 900A, ISD < 15A, 7mm x 8mm QFN52 95% Efficiency, VIN: 4V to 24V, VOUT(MIN) = 0.6V, IQ = 900A, ISD < 15A, 9mm x 9mm QFN64 95% Efficiency, VIN: 4V to 32V, VOUT(MIN) = 0.6V, IQ = 900A, ISD < 15A, 9mm x 9mm QFN64
3605fa
20 Linear Technology Corporation
(408) 432-1900
LT 0309 REV A * PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
FAX: (408) 434-0507 www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2009

▲Up To Search▲

Price & Availability of LTC3605

	To Download LTC3605 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .